1. Field of Invention
The present invention relates to electronic circuit designs, and amongst other things to a method and apparatus for entering, saving, sharing, and displaying connections in an electronic design. The invention also relates to entry and display of connections in any type of network.
The invention can also be leveraged in a large pin-count Integrated Circuit Package design where the connectivity from the die to the package is defined.
2. Discussion of Background
Modern circuit design, particularly board-level digital designs, is not as efficient as it was when schematic capture techniques were first utilized. Designs once consisted of many small and medium pin-count devices with an occasional large FPGA, MCM, or connector. For small and medium pin-count devices one schematic symbol has sufficient space for identifying all pins and signals associated with the device and it could be easily placed on an A or B size page. However, modern designs are increasing in complexity and decreasing in the number of components on the board being designed. The increased complexity is realized in the size of the ICs, FPGAs, ASICs, and other large components now placed on the board. Large components with hundreds, or even a thousand or more pins is not uncommon. Therefore, as the complexity of the component increases along with increased pin counts, there is also a corresponding increase in the complexity of the logical interconnects between the components and other components/devices on the board.
As a result, using traditional schematic design approaches, a large majority of schematics have become little more than many large rectangular schematic symbols with pin stubs and signal names attached (one block with wires and signal names attached to it). In the larger designs (e.g., a 1,000 pin FPGA) is so large that the single device will not fit on a standard sized schematic page. To get around this problem, using current schematic techniques, the larger devices are split into multiple parts of a schematic symbol, the multiple parts are then individually placed on multiple sheets of schematic drawings.
Furthermore, as large pin count devices become more prevalent in designs, there is a need to be able to connect these up quickly. And, instantiating these in schematics has following additional pitfalls:
Schematic symbol creation is often needed, particularly for large pin-count devices. Even though library tools are becoming more and more mature in their abilities to import XML, apply symbol templates and create multiple symbols, the process is not always usable for a specific device or component (particularly newly developed components). Some devices simply do not have XML or other import representations.
Symbol graphics do not necessarily represent the logical function of a device. The symbol has to be split into multiple symbols because it is too big to fit on a single schematic sheet. Some users spend great amounts of time documenting the function of a device by annotating graphics inside the device boundary. This is extremely time consuming and not always an effective way of describing the logical intent.
Large symbol instances leave little room for logical wiring. This means that all connections are formed via signal names. This is an error-prone process and is time-consuming to capture.
Designers have entered their connectivity in Verilog™ and have written custom parsers to parse these files and create connectivity files for layout tools. However, entering connectivity in Verilog™ is also error prone as the user enters all pin names manually and then enters the signal names. With large FPGAs or other ICs, the chances for error are significant. Furthermore, there are difficulties for user attempting to see his/her packaging information, like reference designators and pin numbers, in the Verilog™ text file. Adding constraints and properties is difficult, and nearly impossible in a standard text editor.
Unfortunately, the available techniques only reduce traditional design to a connect-by-name process instead of connect by logical wire. And again, very few of the symbol's graphics indicate any logical meaning, which makes it more difficult for a designer to capture the larger picture of what the design is intended to produce. This is quite different than what the schematic illustrations are able to convey when entire symbols, and, in fact, entire designs were placed on a single, or a relatively small number, of schematic sheets. When able to “see” more of the entire design, the designer has a better understanding of the goals of the design and can more quickly decide what modifications/improvements are needed to complete or improve a particular design. Therefore, designer productivity and quality improvements can be made if tools are available that allow designers to more easily capture and then comprehend and understand the myriad of connections required in modern circuit designs.